1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device including a detection circuit for detecting a state of an input signal.
2. Description of the Related Art
A signal input of a semiconductor device such as a dynamic random access memory (DRAM) is performed using a clock signal of a system including the semiconductor device. If the clock signal is changed by an internal noise or an external noise, an accurate signal may not be inputted to the semiconductor device. Moreover, if an input signal does not have a sufficient margin to be synchronized with the clock signal, the input signal may not be accurately inputted to have an influence on an output signal. Since such an output signal of a logic circuit is not identified in a typical system configuration, another logic circuit using the output signal as an input signal may malfunction. It is referred to as ‘metastable state’ the output signal of which is not determined as a logic high level or a logic low level.
FIG. 1A is a circuit diagram illustrating an output circuit having a plurality of synchronization units, and FIG. 1B is a timing diagram explaining a metastable state of the output circuit shown in FIG. 1A.
Referring to FIG. 1A, the output circuit includes a plurality of synchronization units, which are serially coupled to each other. The plurality of synchronization units receive an input signal and a clock signal CLK, synchronize the input signal with the clock signal CLK, and output a synchronized input signal as an output signal. As the input signal, the first one of the plurality of synchronization units receives an input signal INPUT and the others receive an output signal of the preceding one. If an output signal outputted from the last one of the plurality of synchronization units is a final output signal OUT, a metastable state may occur in the input signal INPUT due to a relative timing margin on a rising edge of the clock signal to the input signal of each of the plurality of synchronization units. For example, in case of a rising-edge triggered flip-flop, an input signal INPUT maintains a data value for a certain time before and after a rising edge of the clock signal CLK. Herein, a data maintaining time prior to the rising edge time of the clock signal CLK is referred to as a setup time, and a data maintaining time posterior to the rising edge time of the clock signal CLK is referred to as a hold time.
Referring to FIG. 1B, an occurrence cause of a metastable state may be recognized from a wave form depending on the input signal INPUT. In case of (a) and (b), a margin is over than the setup time and the hold time. If the input signal having a logic high level is inputted, an output signal of the synchronization unit has a logic high level. If the input signal having a logic low level is inputted, the output signal of the synchronization unit has a logic low level. On the contrary, in case of (c), (d) and (e), since the input signal does not satisfy the setup time and the hold time, the output signal may have a metastable state or a little transition slope. If such an unstable signal is inputted, the final output signal OUT may have an unstable output value instead of a level of the input signal. Because of such a final output signal OUT, an operation error may occur in a memory system.